1. Field of the Invention
The present invention relates to a multilayer chip capacitor and, more particularly, to a multilayer chip capacitor that can be suitably used as a decoupling capacitor of a power distribution network of a micro-processor unit (MPU) and reduce, as a single capacitor, impedance of the power distribution network to a target impedance or less in a broad frequency range of hundreds of kHz to hundreds of MHz.
2. Description of the Related Art
Designing a power distribution network (PDN) of a microprocessor unit (MPU) is increasingly difficult as the MPU becomes faster in speed and more integrated. In particular, a decrease in a power voltage and an increase in current consumption of the MPU resulting from the integration of the MPU lead to a gradual lowering of a target impedance (Ztarget) as represented by equation shown below:Ztarget=Vp×AR/I=Vr/I 
In the equation, Vp is a power voltage, AR is an allowed ripple, ‘I’ is a current consumption of the MPU, and Vr is an allowed ripple voltage. Generally, the allowed ripple voltage Vr is about 5% to 10% of the power voltage. The target impedance (Ztarget) should be satisfied not only in a direct current (DC) but also in all frequencies where transient current is present. In case of a personal computer (PC) or a notebook computer, as its CPU (MPU chip) operates at a high speed, a transient current exists even at a very high frequency range, and thus, a target impedance should be satisfied even in a broad frequency range. In order to satisfy the target impedance in each frequency range, the PDN employs a voltage regulator module (VRM), a bulk capacitor, a general two-terminal multilayer chip capacitor (MLCC), and a low equivalent series inductance (ESL) MLCC, and such PDN is called a multi-stage PDN.
The VRM, the bulk capacitor, and the general two-terminal MLCC serve to supply current in a frequency range of a few kHz, a few kHz to hundreds of kHz, and hundreds of kHz to a few Mhz, respectively, and lower impedance of the PDN. Unlike a bulk capacitor or the general two-terminal MLCC directly mounted on a motherboard, the low ESL MLCC is generally mounted on a CPU package, supplies current in a frequency range of a few MHz or higher, and serves to lower the impedance of the PDN. Finally, at a frequency higher than the valid frequency range of the low ESL MLCC, a die capacitor within a CPU supplies current and lowers the impedance of the PDN. The plurality of above-mentioned bulk capacitors, the general two-terminal MLCC, and the low ESL MLCC are connected in parallel to each other by using an R-L-C model.
FIG. 1 is a graph of the magnitude of impedance (Z) versus frequency of a general multi-stage PDN. In each stage, the impedance ZREG, ZBLK, ZMF, ZPKG, and ZDIE Of the VRM, bulk capacitor, general 2-terminal MLCC, low ESL MLCC and die capacitor determines the overall impedance of the PDN, and accordingly, it is noted that the impedance of each capacitor considerably affects an impedance profile of the entire PDN. In addition, an impedance of a previous stage capacitor is associated with that of a next stage capacitor to determine the overall impedance of the PDN. In designing the PDN, the impedance of each stage cannot be independently determined but should be determined in consideration of the overall impedance of the PDN. In general, the two-terminal MLCC having a relatively high ESL is mounted on the motherboard or the CPU package and used for mid-frequency decoupling, and the low ESL MLCC is mounted on the CPU package and used for high-frequency decoupling.
FIG. 2 is a cross-sectional view schematically showing a related art motherboard device with decoupling capacitors and MPU wiring connection structure (i.e., line connection structure). With reference to FIG. 2, a CPU (i.e., MPU chip) 51 is mounted on a package board 53 to form a CPU package 51 and 53, and the CPU package 51 plus 53 is surface-mounted on a motherboard 55. Wiring conductors, e.g., power (PWR) planes, ground (GND) planes, vias, and the like, are formed within and on the surface of the motherboard 55 and the package board 53 to configure a power circuit. Bumps or balls 15 are used to electrically connect the components 53 and 55. Different types of decoupling capacitors 10 and 20 are connected to such power circuit by frequency ranges to form the multi-stage PDN. The low ESL MSCC 10 for high-frequency decoupling, e.g., a low inductance ceramic capacitor (LICC) or an interdigital capacitor (IDC), may be mounted on a lower surface of the board 53 of the CPU package. The general MLCC 20 for mid-frequency decoupling may be directly mounted on an upper or lower surface of the motherboard 55 in the vicinity of the CPU package 51 plus 53, or may be mounted on the lower surface of the CPU package board 53.
As described above, in order to form the multi-stage PDN, the capacitors 10 and 20 of different structures are used according to each frequency range. Thus, different capacitor mounting surfaces or mounting portions should be provided by frequency ranges, and a large number of chip capacitors 10 and 20 are needed to lower the overall PDN impedance to below a target impedance.